Sense amplifier systems and a matrix-addressable memory device provided therewith

ABSTRACT

A sense amplifier system for sensing the charge of a charge-storing means ( 601 ) comprises first and second charge reference means ( 600   a   ,600   b ) connected in parallel and similar to the charge-storing means itself and having respectively opposite polarizations. The charge reference means ( 600   a   ,600   b ) and the charge storing means ( 600 ) have a common input node (WL), and first and second pseudo-differential reference sense amplifiers (RSA 1 , RSA 2 ) are connected with output nodes (RBL 1 , RBL 2 ) of the charge reference means ( 600   a   ,600   b ) for generating reference signals to a common reference node (CHREF) connected with a pseudo-differential sense amplifier (SA). The pseudo-differential sense amplifier (SA) has a second input for receiving an output signal from the charge-storing means ( 601 ) and generates an output signal indicative of a polarization state of the charge-storing means. Another sense amplifier system is generically similar, but adapted for sensing the charges of a plurality of charge-storing means ( 701 ) and comprises for this purpose at least two pairs of charge reference means ( 700 ). The charge-storing means ( 701 ) form the elements in an orthogonal matrix such that all elements in a row are connected with a pseudo-differential sense amplifier (SA). This sense amplifier system is implemented in a non-volatile matrix-addressable memory device comprising an electrical polarizable dielectric memory material exhibiting hysteresis, particularly a ferroelectric or electret material. The memory cells ( 801 ) of the memory device can be selectivly addressed for a write/read operation and the sense amplifier system (SA) is used for readout of polarization states of the memory cells.

The present invention concerns a sense amplifier system for respectivelysensing the charge of a passive addressable charge-storing means, andfor sensing the charges of a plurality of passive-addressablecharge-storing means.

The present invention also concerns a non-volatile passivematrix-addressable memory device comprising an electrically polarizabledielectric memory material exhibiting hysteresis, particularly aferroelectric or electret material, wherein said memory material isprovided in a layer contacting a first set and second set of respectiveparallel addressing electrodes, wherein the electrodes of the first setconstitute word lines of the memory device and are provided insubstantially orthogonal relationship to the electrodes of the secondset, the latter constituting bit lines of the memory device, whereinmemory cells with a capacitor-like structure are defined in the memorymaterial at the crossings between word lines and bit lines, wherein eachmemory cell can be selectively addressed for a write/read operation viaa word line and bit line, wherein a write operation to a memory celltakes place by establishing a desired polarization state in the cell bymeans of a voltage being applied to the cell via the respective wordline and bit line defining the cell, wherein said applied voltage eitherestablishes a determined polarization state in the memory cell or isable to switch between the polarization states thereof, and wherein aread operation takes place by applying a voltage to the memory cell anddetecting at least one electrical parameter of an output current on thebit lines, and wherein a sense amplifier system according to theinvention is provided for sensing said polarization states of saidmemory cells during a read operation.

Ferroelectrics which property constitutes a subclass of electrodes areelectrically polarizable materials that possess at least two equilibriumorientations of the spontaneous polarization vector in the absence of anexternal electrical field, and in which the spontaneous polarizationvector may be switched between those orientations by an electric field.The memory effect exhibited by materials with such bistable states ofremanent polarization can be used in memory applications. One of thepolarization states is considered to be a logic “1” and the other alogic “0”. Typical passive matrix addressing memory applications areimplemented by letting two sets of parallel electrodes cross each other,normally in an orthogonal fashion, in order to create a matrix ofcross-points that can be individually accessed electrically by selectiveexcitation of the appropriate electrodes from the edge of the matrix. Alayer of ferroelectric material is provided between the electrode setsin a capacitor like manner so that the cross-points can function asmemory cells. When applying potential differences between twoelectrodes, the ferroelectric material in the cell is subjected to anelectric field which generates a polarization response generally tracinga hysteresis curve or a portion thereof. By manipulating the directionand the magnitude of the electric field, the memory cell can be left ina desired logic state. The passive addressing of this type ofarrangement leads to simplicity of manufacture and a high density ofcross-points.

One set of parallel electrodes is usually referred to as word lineswhile the other set is referred to as bit lines. The electroniccircuitry performs drive and sense operations on the memory matrix byemploying a timing sequence that consists of a voltage vs. timeprotocol. Potentials on selected word and bit lines are controlled so asto approach or coincide with one of a few predefined potential levelsduring the drive and sense operations. The bit lines are furtherconnected to circuitry that senses the charges flowing between the bitlines and the cells connecting to said bit lines within a certain periodof the timing sequence. This latter circuitry includes sense amplifiers.Sense amplifiers generally compare the polarization response of memorycells to the value of a voltage or charge reference. A number ofdifferent techniques can be used to create the reference value. Assumingstable and predictable conditions, a parasitic contribution may inprinciple be removed by subtracting a fixed amount of charge from thatrecorded by the sense amplifier during the reading cycle. However, themagnitude and variability of the parasitic contribution makes thisinappropriate in many instances. In addition to manufacturingtolerances, the fatigue and imprint history may vary within wide limitsbetween different cells in the same memory device and the parasiticcurrent associated with the active bit line may depend on the actuallogic states of the non-addressed cells on that bit line. Thus,reference levels can be obtained from neighbouring cells to deal withthese problems.

A reference voltage circuit used for determining the polarization stateof a ferroelectric capacitor is presented in U.S. Pat. No. 5,218,566(Papaliolios). The circuit includes a pair of ferroelectric capacitors,each polarized to an opposite polarization state, that discharge theirstored charges into respective sense capacitors. By short-circuiting thesense capacitors a reference voltage is obtained that can be used tocompare memory cell signals generated by other ferroelectric capacitors.U.S. Pat. No. 5,999,439 (Seyyedy) describes a similar approach wherein amultiplexed sense amplifier is used to compare data stored on a memorycell with a single-ended reference voltage generated from a pair ofreference cells. However, both these circuits have active matrixaddressing memories which makes the requirements on the sense amplifiersless demanding. In a passive matrix addressing memory there aresignificantly lower input signals, and neither Papaliolios nor Seyyedyteach any solution to this problem.

A pseudo-differential sense amplifier is described in U.S. Pat. No.5,572,474 (Sheen & al.) that senses the state of an array memory cell byreference to reference cell in a predetermined state. The senseamplifier has an input stage coupled to the array memory cell, whichprovides signals to a differential stage from which an output isgenerated. The input stage has reference and array side cascode circuitsin which the components are matched on each side so as to eliminateprocess, temperature, and other extraneous variations from influencingthe differential output. However, the teachings of Sheen et al. arereliant on the benefit of a MOS transistor's gain and do not achieve theauto-zero offset cancellation and excellent charge balance needed.

U.S. Pat. No. 5,638,322 (Lacey) describes a pseudo-differential senseamplifier having improved common-mode noise rejection. The senseamplifier is connected to a memory cell via an array path and generatesan output signal indicative of the state of the memory cell. The senseamplifier includes an array load device connected via an array node tothe array path, a reference load device connected via a reference nodeto a reference path, a differential stage having a first input connectedto the reference node, a second input connected to the array node and anoutput generating the output signal. The sense amplifier furtherincludes a balancing device, connected to the reference node, forcompensating a change in signal, caused by a noise event, at the arraynode and, thus reducing a delay in the response of the sense amplifierwhen a transition in the state of the cell occurs. However, the memoryelement is a MOSFET that amplifies the signal and Lacey does not teachhow to achieve a pseudo-differential sense amplifier with gain andaccuracy for the requirements of a ferroelectric memory.

Thus it is a primary object of the present invention to provide senseamplifier systems that is particularly suited for use with polymerferroelectric memory material in the form of thin films, as well as anon-volatile passive matrix-addressable memory device employing one suchsense amplifier system.

Particularly it is an object of the invention to provide a senseamplifier system of this kind with improved charge balance when areference voltage is generated by using a pair of ferroelectriccapacitors, each polarized to an opposite polarization state.

More particularly it is an object of the present invention to provide asense amplifier system which shall be able to control output common-modevoltage and common-mode self-bias generation as well as auto-zero offsetcancellation.

The above objects as well as further features and advantages are alsorealized according to the invention with a sense amplifier system whichis characterized in comprising a pair of a first and second chargereference means connected in parallel and similar to the charge-storingmeans, said first charge reference means having the oppositepolarization of the second charge reference means, said first and secondcharge reference means and the charge-storing means having a commoninput node; first and second pseudo-differential reference senseamplifiers being connected with an output node of one of the chargereference means, said first and second pseudo-differential amplifiersbeing adapted for generating output reference signals to a commonreference node; and a pseudo-differential sense amplifier having a firstinput connected with the common reference node for receiving a commonreference input signal and a second input for receiving an output signalfrom the charge-storing means; whereby the pseudo-differential senseamplifier is enabled to perform a threshold comparison and generating anoutput sense signal indicative of a polarization state of thecharge-storing means.

In this sense amplifier system both the pseudo-differential referencesense amplifier and the pseudo-differential sense amplifiers areidentical pseudo-differential sense amplifier circuits.

Preferably each pseudo-differential sense amplifier circuit comprisesinput differential pair transistors connected with a pair of cascodedtransistors, and current source biasing pair transistors cascoded with apair of transistors, said cascoding in each case increasing senseamplifier open-loop gain. The input transistors can then be p-channeltransistors and the current-source transistors n-transistors or viceversa.

Preferably each pseudo-differential sense amplifier circuit comprises asemi-balanced dual input with balanced dual output.

Preferably each pseudo-differential sense amplifier circuit comprises aswitched capacitor common feed-back loop to control output common modevoltage.

Preferably each pseudo-differential sense amplifier circuit comprisesmeans for integral switched capacitor common mode self-bias generation.

Preferably each pseudo-differential sense amplifier circuit comprises anintegral positive feed-back latch.

Preferably each pseudo-differential sense amplifier circuit comprisesmeans for auto-zero offset cancellation.

The above objects as well as further features and advantages are alsorealized according to the invention with a sense amplifier system whichis characterized in comprising at least two pairs of a first and asecond charge reference means similar to the charge-storing means, saidfirst charge reference means having the opposite polarization of thesecond charge reference means; each of said at least two pairs of chargereference means having a common input node and a pair of common outputnodes connected with said first and said second charge reference meansin each of said at least two pairs thereof, each common input node ofsaid at least two pairs of charge reference means moreover beingconnected with at least two charge storing means; first and secondpseudo-differential reference sense amplifiers being respectivelyconnected with the first common output node and the second common outputnode of the charge reference means, said first and secondpseudo-differential reference sense amplifiers being adapted forgenerating output reference signals to a common reference node; and atleast two pseudo-differential sense amplifiers, each having a firstinput connected with said common reference node for receiving a commonreference input signal and a second input respectively being connectedwith a common output node of respective one of said at least twocharge-storing means for receiving respective output signals therefrom,said at least two charge-storing means forming the elements of anorthogonal row and column array thereof and with each of thecharge-storing means of a row being connected to one of said at leasttwo common input nodes and each of the charge-storing means of a columnbeing connected to a common output node; whereby eachpseudo-differential sense amplifier is enabled to perform a thresholdcomparison and generating an output sense signal indicative of apolarization state of a selected charge-storing means connectedtherewith.

In a preferred embodiment of the latter sense amplifier system thecommon input nodes form a portion of the word-line electrodes of amatrix-addressable array of charge-storing memory cells, the commonoutput nodes of the charge reference means form a pair of referencebit-line electrodes; the common output nodes of the charge storing meansform bit-line electrodes of said matrix-addressable array; each of thereference bit-line electrodes are assigned to the first and secondpseudo-differential reference sense amplifiers respectively; and each ofthe other bit-line electrodes are assigned to one of thepseudo-differential sense amplifiers, whereby in a readout cycle apolarization state of respective selected charge-storing memory cellscan be detected either sequentially or in parallel and compared with areference value.

In this preferred embodiment the sense amplifier system advantageouslycan be provided as a subblock in block of more than one sense amplifiersystems of this kind, such that the sense amplifiers of a subblock areassigned to a corresponding number of bit line electrodes in thematrix-addressable array; and the pair of reference bit lines ofrespective subblocks are distributed among the bit lines of array.Alternatively the sense amplifier system advantageously can comprise amultiplexer connected with the bit line electrodes of thematrix-addressable array; a number of consecutive bit lines in the arraydefining a segment of all word line electrodes therein, said number ofsegment-defining bit lines corresponding to the number ofpseudo-differential sense amplifiers in the sense amplifier system; anda pair of reference bit line electrodes provided adjacent to the bitline electrodes in each word line segment and connecting pairs ofreference charge-storing means in each word line segment; whereby thecharge-storing memory cells on a single word line electrode of a wordline segment may be read in parallel, and all word line segmentssimilarly in turn by applying an appropriate addressing protocol andmultiplexing the bit line electrodes of selected word line segment toestablish their parallel connection to respective pseudo-differentialsense amplifiers of the sense amplifier system as provided.

Finally, the above-mentioned objects as well as further features andadvantages are realized according to the invention with a non-volatilematrix-addressable memory device which is characterized in that thesense amplifier system is a pseudo-differential sense amplifier systemcomprising at least one system subblock, and that said at least onesystem subblock comprises at least one pseudo-differential senseamplifier circuit for sensing a polarization state of at least onememory cell during said read operation and at least onepseudo-differential reference sense amplifier circuit for sensingpolarization state of at least one reference memory cell during saidread operation, said at least one former circuit being connected withsaid at least latter circuit via a common node.

In an advantageous embodiment of the memory device according to thepresent invention the at least one system subblock comprises a pluralityof said pseudo-differential sense amplifier circuits for sensingrespective polarization states of a corresponding a plurality of memorycells during said read operation.

In another advantageous embodiment of the memory device according to thepresent invention the at least one system subblock comprises tworeference sense amplifier circuits for sensing two reference memorycells during said read operation, said reference ferroelectric memorycells having opposite polarization states, and preferably are then thefirst and second reference amplifier circuits adapted for generating anaverage of a first and a second reference memory cell output signal tosaid common node; and the at least one sense amplifier circuit connectedtherewith is adapted for comparing the output signal at said common nodewith the output signal from a memory cell.

Advantageously the at least one sense amplifier circuit and the at leastone sense amplifier circuit are realized with identical amplifiercircuitry, and then preferably the identical amplifier circuitry thencomprises a reference side and an array side, said reference sidemirroring the circuit structure of said array side.

In a further advantageous embodiment of the memory device according tothe invention the pseudo-differential sense amplifier system comprises aplurality of subblocks.

In a yet further advantageous embodiment of the memory device accordingto the invention each subblock comprises a plurality of said senseamplifier circuits for sensing the polarization state of a correspondingnumber of memory cells.

The present invention shall now be explained in greater detail by meansof a discussion of exemplary embodiments thereof and in conjunction withthe appended drawing figures, of which

FIG. 1 shows a schematic hysteresis curve of a ferroelectric memorymaterial,

FIG. 2 a a principle drawing of a passive matrix-addressing arrangementwith crossing electrode lines,

FIG. 2 b a principle drawing of a passive matrix with cells containingferro-electric material localized between the overlap of crossingelectrode lines,

FIG. 3 a block diagram of a memory device according to the presentinvention,

FIG. 4 a circuit diagram of a preferred embodiment of apseudo-differential sense amplifier circuit according to the presentinvention,

FIG. 5 a block diagram of a pseudo-differential sense amplifier systemaccording to the present invention,

FIG. 6 a schematic block diagram of a general pseudo-differential senseamplifier system according to the invention,

FIG. 7 a sense amplifier system according to the invention as providedin a passive matrix arrangement with crossing electrode lines similar tothe arrangement shown in FIG. 2 a and with charge-storing meansconnected between the crossing electrode lines,

FIG. 8 the sense amplifier system according to the invention and asprovided in a first embodiment of a passive matrix-addressable memoryaccording to the invention, and

FIG. 9 a sense amplifier system according to the invention and asprovided in a second embodiment of a passive matrix-addressable memoryaccording to the invention.

Before the present invention is explained with reference to preferredembodiments, a brief review of its general background shall be givenwith particular reference to the hysteresis of ferroelectric materialsand the structure of matrix-addressable ferroelectric memories.

Referring to FIG. 1, a material with a hysteresis curve 100 changes itspolarization direction upon application of an electric field thatexceeds the coercive field E_(C). The hysteresis curve is shown with thevoltage rather than the field along the abscissa axis for reasons ofconvenience. The voltage is calculated by multiplying the field with thethickness of the ferroelectric material layer. A saturationpolarization, P_(S), occurs whenever a cross-point, i.e. a memory cell,is subject to the nominal switching voltage Vs. Once the electric fieldis removed the polarization will return to one of two remanentpolarization states +P_(R) at 110 and −P_(R) at 112.

FIG. 2 a shows a matrix of orthogonally intersecting electrodes lines.In order to conform to standard terminology, it is henceforth referredto the horizontal (row) electrode lines as word lines 200, abbreviatedWL and to vertical (column) electrode lines as bit lines 210,abbreviated BL. During the drive and sense operations a selected wordline 202 and one or more bit lines 212 are activated. It is desired toapply a voltage that is sufficiently high to switch a given memory cell220, see FIG. 2 b, either for defining a given polarization direction inthat cell (writing), or for monitoring the preset polarization direction(reading). The ferroelectric material layer located between theelectrodes 200, 210 functions like a ferroelectric capacitor 222.Accordingly, the cell 220 is selected by setting the potentials of theassociated word line 202 and bit line 212 (the active lines) such thatthe difference equals the nominal switching voltage Vs. At the sametime, the numerous word lines 200 and bit lines 210 that cross at cells220 not addressed must be controlled in potential such that thedisturbing voltages at these cells 220 are kept to a minimum.

It may be useful to review the overall function and structure of thepassive matrix-addressable memory device in a generalized manner, withreference to FIG. 3 and which in the following by way of example isreferred to as a ferroelectric memory, as generally known in the art,while according to the invention pseudo-differential sense amplifiersthen are used for sensing the polarization states of ferroelectricmemory cells.

FIG. 3 shows in a simplified block diagram form, the structure and/orfunctional elements of a matrix-addressable ferroelectric memory deviceaccording to the present invention. The memory macro 310 consists of amemory array 300, row and column decoders 32; 302, sense amplifiers 306,data latches 308 and redundant word and bit lines 304; 34. The memoryarray 300 contains the matrix of word lines 200 and bit lines 210. Therow and column decoders 32; 302 decode the addresses of memory cellswhile sensing is performed by the sense amplifiers 306. The data latches308 hold the data until part or all of the data is transferred to thememory control logic 320. The data read from the memory macro 310 willhave a certain bit error rate (BER) which can be decreased by replacingdefective word and bit lines in the memory array 300 with redundant wordand bit lines 304; 34. In order to perform error detection the memorymacro 310 may have data fields containing error correction code (ECC)information. The memory control logic 320 module provides a digitalinterface for the memory macro 310 and controls the reads and writes ofthe memory array 300. Memory initialisation and logic for replacingdefective bit and word lines with redundant word and bit lines 304; 34will be found in the memory control logic 320 as well. The devicecontroller 330 connects the memory control logic 320 to external busstandards. A charge pump mechanism 340 generates some of the voltagesneeded to read and write the memory cells.

Specific and preferred embodiments as applied to storing and readingdata to and from ferroelectric memory cells as have been discussed inthe foregoing, shall now be described in relation to the more generalproblem of sensing the much smaller signals that result from reading ofmemory cells in passive matrix addressing memories. Particularly thistrait is manifest in the difference in magnitude of the backgroundcurrents in the active bit line and the charge emanating from an activecell being read.

The general solution to inaccurate amplification of the minute inputsignals as proposed by the present invention is to introduce anelaborate higher-gain switched-capacitor with auto-zero offsetcancellation and excellent charge balance. This presupposes that areference voltage is formed by using a pair of ferroelectric capacitors,each polarized to an opposite polarization state. The single-endedreference voltage generated from the reference cells can then be used tofacilitate the comparison of memory cell signals generated by otherferroelectric capacitors since the background currents can be moreeasily compensated for.

The sense amplifier system as used with the memory device according tothe invention shall now be described in greater detail with reference toFIGS. 4 and 5. FIG. 4 shows a circuit diagram of a pseudo-differentialsense amplifier circuit and this sense amplifier circuit corresponds tothe sense amplifier used in a sense amplifier system according to theinvention as depicted in FIG. 5 wherein the sense amplifier circuits aredenoted by the op-amp blocks 500, 502, 504. In FIG. 5 the op-amp blocks502 and 504 represent two reference amplifiers which are connected inparallel. Two reference bit lines 508, 510 are joined together at theshared input viz. nodes INR of the two reference sense amplifiers 502,504. Just prior to the read operation one of the two reference bit lineelements 514 a; 516 a is written a logic 1 and the other is written alogic 0. Then during the read operation, the resulting voltage at nodeCHREF will therefore represent an average of a logic 1 and a logic 0state. The resulting so-called charge reference at node CHREF is furtheramplified by the primary sense amplifier 500. The gain from node CHREFto the differential output V_(outdiff)=SA_(outp)−SA_(outm) is such thatthe reference level given by the difference V_(outdiff) will offset thecharge injected by the active element at node INR by one-half of thevoltage difference between a logic 1 and a logic 0. Under the assumptionof a good matching between the bit line capacitance and theferroelectric charge the V_(outdiff) voltage corresponding to an activeto a logic 1 and a logic 0 on an active bit line BL will be central at 0V. In this manner a memory element in the logic 1 state will have aV_(outdiff)>0 and an element in the logic 0 state a V_(outdiff)<0. TheV_(outdiff) voltage is then latched to detect a logic statecorresponding to the read data bit.

It is to be understood that the sense amplifier system in FIG. 5 maycomprise a large number n of sense amplifiers 500 and hence element 530in FIG. 5 represents the load capacitance of the not shown n−1 senseamplifiers identical to sense amplifier 500. In a practical embodimenthence the sense amplifier system as depicted in FIG. 5 has one nodeCHREF which is connected in common to e.g. 32 active sense amps 500. Inother words FIG. 5 represents a block of one node CHREF connected to nactive sense amps 500. It is to be understood that n can be chosensuitably large so that the sense amplifier system as used in theinvention may contain a very large number of sense amplifiers 500sharing the same node CHREF and two reference amplifiers 502, 504.Moreover each memory device may comprise a plurality of sense amplifiersystem subblocks identical to the one shown in FIG. 5.

Now the circuit diagram of a pseudo-differential sense amplifier similarto one of the op-amp blocks 500, 502, 504 in FIG. 5 shall be describedwith reference to the circuit diagram in FIG. 4 which shows the circuitlayout of a single pseudo-differential sense amplifier. It is to beunderstood that the circuit diagram in FIG. 4 is rather schematic andhence includes parasitic elements, which not at all are related to thecircuit functionality. For instance the diodes 470 a,b,c,d,e,f groundedrespectively at 460 a,b,c,d,e,f can be regarded as parasitic devicesonly and are in no way central to the operation of the sense amplifiercircuit as such.

In a generally preferred embodiment of the present invention, theproblem of having large background currents and small input signals isaddressed by implementing pseudo-differential sense amplifiers whichhave balanced and symmetrical design. This shall now be explained withreference to the circuit diagram of the pseudo-differential senseamplifier in FIG. 4. In that connection the designation of the variousnodes depicted in this figure shall also be used for referring to thevoltages on these nodes.

A bias voltage V_(biasp) is provided at the gate of current sourcetransistor 400. The p-type current source transistor 400 has its sourceand substrate coupled to a voltage supply line V33. The drain oftransistor 400 provides bias current to the common-source connection ofp-type input differential-pair transistors 402, 404. To help minimizethe die area, p-channel devices share common NWELL bodies wherever thebiasing requirements for proper functionality allow. Hence, transistors400, 402, and 404 share a common body that is contacted to line V33. TheINP and INM inputs are coupled to the gates of the inputdifferential-pair transistors 402 and 404 respectively. The drains ofthe input differential-pair transistors 402 and 404 drive the sources ofthe cascode stage transistors 410 and 412 respectively. This cascodestage dramatically improves the open-loop gain of the sense amp.Similarly, n-channel current-source biasing transistors 438 and 440 arecascoded with n-channel transistors 434 and 436 which also improves thesense-amplifier open-loop gain. The sense-amplifier output is taken asthe difference between nodes OUTP and OUTM. The difference signal(OUTP-OUTM) is the voltage corresponding to the integrated chargedifference between the active bit line (node ‘IN’ of FIG. 5) and thecharge reference bit lines (nodes ‘INR’ of FIG. 5) at the end of a readcycle. p-channel transistors 406, 408, 422, 424, 426, 428 are allutilized as simple two-terminal MOS capacitors in the design of FIG. 4.Capacitive transistors 426, 428 provide common-mode feedback to thegates of current-source transistors 438, 440 at node VCM. Duringcharge-integration, the VCM voltage is proportional to the common-modeoutput voltage (OUTP+OUTM)/2. Negative feedback through capacitivetransistors 426, 428 at node VCM to the gates of current-source devices438, 440 controls and maintains the common-mode output voltage duringcharge integration. In connection with the above discussion it should benoted that the input transistors equally could be n-channel transistorsand the current source transistors p-channel transistors. In otherwords, the circuit implementation is not dependent on the conductionmode of the transistors in a given context, as long as the circuitfunctionality is maintained.

It will be seen that the pseudo-differential sense amplifier circuitcomprises a switch capacitor common-mode feedback loop to control theoutput common-mode voltage. In other words, the common-mode feedbackloop consists of capacitive elements or transistors 426, 428, n-channelcurrent-source transistor 438, 440, 434, 436, and n-channel switchtransistors 430, 432. At the start of each read cycle, switchtransistors 430, 432 are closed (the voltage on nodes CMCP and CMCM ishigh) which nulls the voltage on the capacitive feedback transistors426, 428. Next, the CMPC and CMCM voltages are pulled to low which turnsoff the switch transistors 430, 432, thereby establishing a capacitivefeedback path from nodes OUTM, OUTP to node VCM and the gates oftransistors 438, 440. Since the capacitive transistors 426, 428 match,only changes in the common-mode output (OUTP+OUTM)/2 will be transferredto node VCM, and the negative feedback thereby keeps the common-modeoutput voltage constant during the read cycle.

Also the pseudo-differential sense amplifier circuit comprises means forintegral switch capacitor common-mode self-bias generation. Thecommon-mode self-bias is generated when the switch transistors 430, 432are closed (nodes CMCP and CMCM are pulled high) at the beginning ofeach read cycle. This establishes a common-mode bias-voltage equal tothe voltage V_(gs) of the current source transistors 438, 440 at nodeVCM.

During the read cycle, the sense amplifier 500 and reference amplifiers502, 504 all function as integrators. The design in FIG. 4 is used forall three amplifiers 500, 502, 504 in FIG. 5. In particular, capacitivetransistor 406 is the integrator feedback capacitor used in the senseamplifiers 500,502,504. During integration, the charge from node INRshown in FIG. 5 is integrated by the reference sense amplifiers 502 and504 (connected in parallel) and is transferred to the respectivetransistors 406 thereof (also connected in parallel) of FIG. 4. Theresulting voltage on the capacitive transistor 406 in each amplifier502, 504 is inverted and buffered, and appears at node CHREF (FIG. 5).Likewise during integration, charge from node IN is integrated by senseamp 500 and is transferred to its capacitive transistor 406. The netresult is that the charge-difference between nodes IN and INR isintegrated and appears differentially as the difference outputSA_(outp)−SA_(outm). This difference is proportional to the chargedifference Q_(inr)−Q_(in).

A dummy integrator feedback transistor 408 is positioned on thereference side of each amplifier 500, 502, 504 in order to improvesymmetry and balance. This p-type dummy transistor, or dummy gatecapacitor, has its gate coupled to ground 462 a and its source, drainand substrate coupled to the OUTM output. An auto-zero plus transistor418 of n-type has its gate coupled to the auto-zero control plus (AZCP)signal, its source coupled to the INM input and its drain coupled to theOUTP output. Similarly, there is an auto-zero minus transistor 416 ofn-type on the reference side with its gate coupled to the auto-zerocontrol minus (AZCM) signal, with its source coupled to ground 462 a andits drain coupled to the OUTM output. The auto-zero transistors 416, 418perform the necessary switching for implementing the auto-zero mode. Ann-type latch transistor 420 has its gate coupled to the latch (LTCH)signal, its source coupled to the INM input and its drain coupled to thegate of a p-type transistor 422 that functions as an MOS capacitorconnected to node OUTM. At the end of the integration period, a logic 1LTCH signal will turn on transistor 420 and connect the capacitivetransistor 422 between nodes INM and OUTM, thereby introducing positivefeedback that will ‘latch’ the output to the proper state. For bettersymmetry, similar transistors 414 and 424 are included, but do notprovide additional positive feedback. As seen from FIG. 5 the LTCHsignal is only utilized in sense amplifier 500. The LTCH signal is neveractivated (and therefore tied to ground) for the reference senseamplifiers 502, 504.

From the above section it will be seen that the pseudo-differentialsense amplifier circuit comprises an integral positive feedback latch,the positive feedback being provided with a capacitive transistor 422and the switch transistor 420. Regenerative positive feedback can beobtained by pulling the LTCH node high at the end of a read cycle. Thiswill turn on the switch transistor 420, thereby providing positivefeedback from the amplifier node OUTM back to the input node INM throughthe gate capacitance of the capacitive transistor 422.

It should be noted that all diodes indicated in FIG. 4 are reversebiased and are included for simulation purposes to more accurately modelthe NWELL capacitance associated with the various p-channel transistors.These diodes can in general be ignored for the purpose of thisdiscussion.

n-channel transistors 430, 432 and are both controlled by the CMC signalof FIG. 5 (CMCP and CMCM are shorted in FIG. 5). Prior to chargeintegration, the voltage on capacitive transistors 426, 428 is zeroed byapplying logic 1 level to CMC which turns on n-channel switches 430,432. Switch transistors 430, 432 are then turned off on the falling edgeof digital control signal CMC. This nulls the voltage on capacitivetransistors 426, 428 thereby establishing the common-mode level at nodesOUTP, OUTM, and VCM.

As mentioned above, there is a common-mode transistor 432 in theamplifier circuit. This n-type transistor receives the common-modecontrol plus signal (CMCP) at its gate while the drain is coupled to theVCM control signal and the source is coupled to the OUTP output andground 460 e via diode 470 e. The common-mode control minus CMCM signalfeeds the gate of another common-mode transistor 430 located on thereference side. This latter n-type transistor has its drain coupled tothe VCM control signal and the source coupled to the OUTM output andground 460 f via diode 470 f.

Cascoding is practiced throughout the pseudo-differential senseamplifier design to the OUTP and OUTM outputs in order to increase theopen-loop gain, as already mentioned. The common-mode feedback to thecommon gate node of the open-loop gain transistors 434, 436, 438, 440controls the current, thereby maintaining output common-mode voltagecontrol. A differential signal across OUTP and OUTM outputs has noeffect on the VCM control signal.

During common-mode self-bias generation or refresh mode, common-modetransistors 430, 432, auto-zero transistors 416, 418 and latchtransistors 414, 420 are all “closed”, which means that the controlsignals AZCP, CMCP, CMCM and LTCH are all in a “high” logic state. Thiswill refresh the common-mode voltage at the INP and INM inputs as wellas at the OUTP and OUTM outputs of the sense amplifier circuit. In anext step, the auto-zero transistors 416, 418 remain “closed” while thesense amplifier circuit is placed in auto-zero mode. The control signalsAZCP and LTCH are in the “high” logic state while control signals CMCPand CMCM switch to the “low” logic state at this point. This operationnullifies the offset of the amplifier circuit. Once it has settled, theamplifier circuit is placed in an amplify mode where the control signalsAZCP, CMCP, CMCM and LTCH are all in a “low” logic state and wherecommon-mode transistors 430, 432, auto-zero transistors 416, 418 andlatch transistors 414, 420 are all “open”. The amplifier circuit willintegrate the difference between the active bit line (the node IN inFIG. 5) and the charge reference (the node CHREF in FIG. 5) while in theamplify mode. The amplify mode ends with the control signal LTCHswitching back to the “high” logic state, thereby creating aregenerative feedback and forcing the output at OUTP and OUTM outputs tolatch based on the sign of the signal.

In connection with output common-mode voltage control and common-modeself-bias generation auto-zero offset cancellation is obtained.Specifically this will take place as follows. At the beginning of eachread cycle node AZCP is pulled high. This closes the switch transistor418 in each sense and reference amplifier, such that a bias voltage isestablished on nodes IN, INR and CHREF and this voltage equals theV_(gs) of current source transistors 438, 440. After nodes CMCP and CMCMare pulled low with node AZCP remaining high, a small input offsetvoltage difference IN−INR=[(IN-CHREF)−(INR−CHREF)] appears between allactive bit lines and their associated reference. Next, after node AZCPis pulled low, this offset voltage difference is sampled and held on thebit line capacitance, thereby initialising the voltage differencebetween the active bit lines and the reference bit lines to the inputoffset voltage of the pseudo-differential sense amplifier circuit. Thiseffectively decreases the sense amplifier offset to an acceptably smalllevel.

FIG. 5 shows a preferred embodiment of a pseudo-differential senseamplifier system for use in the present invention and capable ofaccurately amplifying a very tiny input signal. It conforms to anelaborate high-gain switched-capacitor with auto-zero offsetcancellation and excellent charge balance.

A first reference bit line 508 and a second reference bit line 510 areshorted together at node INR. The reference bit lines 508, 510 includesreference memory cells 514 a, 514 b, 516 a, 516 b and grounds 514 c, 516c. The combination of reference memory cells 514 b, 516 b and grounds514 c, 516 c correspond to inactive word lines 200. A supply voltage VSis fed to reference memory cells 514 a, 516 a of the active word lines202. The INR node is amplified by the two reference amplifiers 502, 504which are connected in parallel and which function as a buffer amplifierfeeding the buffered INR signal to node CHREF. The two referenceamplifiers 502, 504 and the first sense amplifier 500 all have astructure corresponding to that described in FIG. 4. The node CHREF,also known as the charge reference node, is the average of the chargeassociated with a logic “1” and a logic “0”. In FIG. 5, the firstreference bit line 508 corresponds to the charge of a logic “0” and thesecond reference bit line 510 corresponds to the charge of a logic “1”.It should be noted that control signals AZCM and LTCH of the tworeference amplifiers 502, 504 are coupled to grounds 528 a, 528 b.

The first reference amplifier 502 in parallel with the second referenceamplifier 504 provide a buffered copy of the INR node to the CHREF nodewhich subsequently serves as a common reference input to a group ofsense amplifiers sharing the same CHREF signal. FIG. 5 shows only afirst sense amplifier 500 from the mentioned group of sense amplifiers.Loading by the other sense amplifiers is included schematically with theCSAIN capacitor 530, schematically comprising capacitor 532 and ground534. The first sense amplifier 500 will then amplify the differencebetween its associated bit line 506, labelled as node IN, and the CHREFnode. The output of the first sense amplifier 500 is takendifferentially between the nodes SA_(outp) and SA_(outm), and isconverted to a digital logic level depending on the sign of thedifference result. The entire group of sense amplifiers will function inthe same manner as the first sense amplifier 500. The associated bitline 506 includes memory cells 512 a, 512 b, signal 518 a and ground 526a. The two latter together form a row decoder 32. The signal 518 a isthe same as the supply signal VS used to charge the reference bit-lineelements.

Further, there is another ground 528 e shorting the AZCM control signalof the first sense amplifier 500. The control signals AZCP, CMCP, CMCMand LTCH of the first sense amplifier 500 are controlled by the digitalcontrol signals 518 b, 518 c, 518 d and the coupled grounds 526 b, 526c, 526 d. Finally, the first sense amplifier 500 and the two referenceamplifiers 502, 504 are provided with a gate source bias voltage fromthe associated arrangement 520, 522, 524 to their respective internalcurrent source transistors 400.

The sense amplifier system as shown in FIG. 5 can be regarded as a moreelaborate version of a general sense amplifier system inpseudo-differential sense amplifiers that can be used in any applicationfor sensing charges or for use with devices where there is anappropriate charge reference. This could of course be the case offerroelectric memories where the memory cells are the individual chargestoring means. The minimalist approach to a sense amplifier system isshown in FIG. 6, which can be regarded as a more generalized version ofsense amplifier system in FIG. 5, but with only a single charge storingmeans or capacitor 601 corresponding to the capacitor 512 a in FIG. 5.First and second charge reference means 600 a, 600 b are connected tothe common input node AWL, which also is the input node of the capacitor601. The charge reference means 600 a, 600 b corresponds to thecapacitors 514 a, 516 a in FIG. 5. The charge references means 600 a,600 b have respective output nodes RBL₁, RBL₂ which are short-cicuitedbetween the nodes INR and connected to input INM on eachpseudo-differential reference sense amplifier RSA₁, RSA₂ which thus areconnected in parallel and of course corresponds to thepseudo-differential sense amplifiers 502, 504 in FIG. 5.

The pseudo-differential reference sense amplifiers RSA₁, RSA₂ have acommon output node CHREF, which is connected with a reference input INPon a pseudo-differential sense amplifier SA. The charge storing means601, the capacitance of which shall be sensed, has an output node ABLconnected to an input on the sense amplifier SA. The connections in thearrangement in FIG. 6 are in all respects similar to those in FIG. 5apart from having only a single charge storing means 600 and a singlepseudo-differential sense amplifier SA.

The sense amplifier system according to the invention and as shown inFIG. 6 can easily be adapted for the detection of charge values orpolarization values of a plurality of charge storing means. This isshown in FIG. 7, which can be regarded as an elaboration of the senseamplifier system according to the invention as shown in FIG. 5. It canalso be regarded as an extension of the sense amplifier system asrendered in FIG. 6, but now being arranged to detect charges stored on aplurality of charge storing means. In FIG. 7 these charge storing meansare provided in the form of capacitors 700, 701 between common inputnodes WL and common output nodes. Charge reference means 700, i.e.capacitors corresponding to the charge reference means 600 a, 600 b inFIG. 6 are connected in pairs with common input nodes WL₁ . . . WL_(m)and have common output nodes RBL₁, RBL₂, while the charge storing meansor capacitors 701 have common output nodes BL₁ . . . BL_(n) as shown.The common output nodes RBL₁, RBL₂ of the charge reference means 700 areconnected with inputs of respective reference sense amplifiers RSA₁,RSA₂ which has outputs connected with the common reference node CHREF.The connections are, apart from pairs of charge reference means 700provided as shown, in all respects similar to those of FIG. 5 and inconformity with this figure a plurality of sense amplifiers SA₁, . . .SA_(n) is provided connected via their inputs IN with the respectivecommon output nodes BL₁, . . . BL_(n) of the charge storing means 701.The common reference node CHREF is connected with input node INP of therespective sense amplifiers SA₁, . . . SA_(n). By comparing FIGS. 5 and7 it will be seen that the latter actually has the same generic layout,but with the individual charge reference means and the charge storingmeans as well as the n sense amplifiers SA specifically depicted.

FIG. 7 shows how the sense amplifier system of the invention is embodiedin a passive matrix-addressable arrangement where the common input nodesWL₁ . . . WL_(m) can be regarded as the word lines and the common outputnodes RBL₁, RBL₂; BL₁, . . . BL_(n) can be regarded of the bit lines inan m·n matrix comprising of course m·n charge storing means 701 whichthen could be the memory cells of the passive ferroelectric memorymatrix, while the appropriate charge references are provides by the mpairs of charge reference means 700 with the respective common outputnodes RBL₁, RBL₂ which are reference bit lines of the memory matrix.

In the above-discussed preferred embodiment of the invention the senseamplifier system as used in the memory device according to the inventioncomprises a sense amplifier block as shown in FIG. 5. This block couldbe termed a subblock of the sense amplifier system, and it will be seenthat if there is only one subblock, the sense amplifier subblock thenwill be identical to the sense amplifier system itself. In general asense amplifier system comprises as many sense amplifiers as there arebit lines in the memory device. In addition there are provided (atleast) two reference bit lines in the memory device and connected withrespectively (at least) two reference amplifiers of the sense amplifiersystem. In practice the sense amplifier system may comprise a pluralityof subblocks and each of these subblocks although not specifically shownin FIG. 5, actually shall contain n sense amplifiers 500 for sensing thepolarization of the memory cells used for data storage, as there inaddition to the sense amplifier 500 depicted will be n−1 senseamplifiers represented by the capacitance 530 and of course connected inthe same manner as 500 via common nodes CHREF to the reference senseamplifiers 502, 504. An arrangement of this kind will be provided for afull row read, i.e. the parallel readout of all memory cells on a singleword line of the memory device. However, an embodiment as shown in FIG.8 is preferable and desirable in order to provide an improvedstabilization of the referencing procedure. This is done by dividing thesense amplifier system into identical subblocks SB, each subblockcomprising a plurality k of sense amplifiers SA connectable to a similarnumber k of bit lines and two reference sense amplifiers RSA₁, RSA₂ ineach subblock SB connectable to respectively two reference bit linesRSBL₁, RSBL₂ adjoining the memory bit lines BL assigned to the subblockSB. The reference bit lines RBL are forming the common output nodes ofrespective pair of reference memory cells 800. Hence with an appropriatenumber q of subblocks SB provided for parallel readout of all memorycells 801 on a single word line WL there will now in addition be pairsP/RBL of reference bit lines RBL, the number q of such pairscorresponding to the number q of subblocks. The effect is of course todistribute the reference bit lines RBL and reference memory cells 800 atspecified positions throughout the memory matrix and increase thereliability of the referencing, as the contributions from sneakcurrents, disturb voltages, parasitic capacitances etc. to the actualpolarization values read out from the memory cells 801 may vary over thememory array.

Each subblock comprises as stated k pseudo-differential sense amplifiersSA and all bit lines BL of the matrix is connected with a respectivesense amplifier such that the embodiment in FIG. 8 comprises k·q=n senseamplifiers.

In many instances, particularly when the size of the memory array islarge, i.e. the number of memory cells provided for data storage islarge, and also with a correspondingly increasing data storage densityobtained by reducing the pitch, i.e. either the distance from a wordline or bit line to the next word line or bit line, including the firstone, or by reducing the size in the memory cells, it shall be desirableto employ a number of sense amplifiers that is some fraction of thenumber n of bit lines in the device. This amounts to a so-calledsegmented word line structure, i.e. each word line WL is divided intosegments comprising a specified number of memory cells and of coursethen the same number of bit lines. This embodiment is shownschematically in FIG. 9, where the memory cells located at word and bitline crossings for clarity's sake are not shown. A sense amplifiersystem (or a single sense amplifier block) will now be provided with anumber k of sense amplifiers SA corresponding to the number k of bitlines BL in each word line segment. A multiplexer MUX or pass gate meansis used for connecting the bit lines BL of each segment to correspondingsense amplifiers SA in the sense amplifier system. Hence all memorycells on a word line segment can be read in parallel, and by e.g.multiplexing, the same sense amplifiers now can be used for readout inparallel of each following word line segment in turn. This, of course,implies that the pair of reference sense amplifiers RSA₁, RSA₂ in thesense amplifier system or block similarly shall be connectable via themultiplexer MUX or pass gate means to the pair P/RBL of reference bitlines RBL for each word line segment. Specifically the arrangement willbe such that the first sense amplifier SA₁ of the sense amplifier systemsenses the first bit line BL₁ in the first word line segment, the firstbit line BL_(k+1) in the second word line segment and so on, the secondsense amplifier SA₂ of the sense amplifier system the second bit lineBL₂ of the first line segment, the second bit line BL_(k+2) of thesecond segment and so on.

It shall be understood that a typical application of the sense amplifiersystem in the memory device according to the invention can involve theuse of a large number of sense amplifier blocks and also the use of alarge number of sense amplifiers in each block, but only one pair ofreference amplifiers in each block. It should also be understood thatthe node CHREF in any case will be common to all sense amplifiers in ablock. It is also to be understood that when using a segmented word linedesign and a multiplexed sense amplifier system as mentioned above, thesense amplifier system also then can be divided into a number ofsubblocks, implying that within each word line segment there can becorresponding numbers of pairs of reference bitlines. Each one of thepair of the reference bit lines is used for addressing a column ofmemory cells defined at the crossings between the reference bit linesand the word lines. The memory cells of the first reference bit line ofthe pair may be written to the logic 1 state, while the memory cells ofthe second reference bit line then are written to the logic 0 state. Indestructive readout, either a polarization reversal or not shall takeplace in the memory cell. In the first case a large output, e.g. currentsignal, is obtained and the second case only a small output signal isobtained. An average of these output signals is generated and comparedwith the actual readout values from the data storing memory cells, thelogic state thereof being given by the output either being larger orsmaller than the average reference value.

Generally two reference cells shall be needed for a full row readout ora full word line segment readout. However, in an embodiment of the senseamplifier system in the memory device according to the invention only asingle reference sense amplifier and a single reference bit line may beenvisaged in the case where memory cells are read randomly and not inparallel. In this case, however, a pre-read cycle must be employedsetting the reference memory cell on the active word line to either ofthe polarization states in turn and obtaining a reference value for eachwhereby the average thereof can be generated and input as a reference tothe sense amplifier.

It will from what is said immediately hereinabove be appreciated bypersons skilled in the art that the preceding detailed discussion of thepreferred embodiment of the sense amplifier system in the memory deviceaccording to the invention has been given by way of example only, andshould be evident that the sense amplifier system can be modified invarious ways without deviating from spirit or the scope of the presentinvention as defined in the claims appended hereto.

1. A sense amplifier system for sensing the charge of a passiveaddressable charge-storing means (601), the system being characterizedin comprising a pair of a first and second charge reference means (600a, 600 b) connected in parallel and similar to the charge-storing means(601), said first charge reference means (600 a) having the oppositepolarization of the second charge reference means (600 b), said firstand second charge reference means (600 a, 600 b) and the charge storingmeans (601) having a common input node (AWL); first and secondpseudo-differential reference sense amplifiers (RSA₁; RSA₂) beingrespectively connected with an output node (RBL₁; RBL₂) of one of thecharge reference means, said first and second pseudo-differentialamplifiers (RSA₁; RSA₂) being adapted for generating output referencesignals to a common reference node (CHREF); and a pseudo-differentialsense amplifier (SA) having a first input connected with the commonreference node (CHREF) for receiving a common reference input signal anda second input for receiving an output signal from the charge-storingmeans (601); whereby the pseudo-differential sense amplifier (SA) isenabled to perform a threshold comparison and generating an output sensesignal indicative of a polarization state of the charge-storing means.2. A sense amplifier system according to claim 1, characterized by boththe pseudo-differential reference sense amplifiers (RSA₁; RSA₂) and thepseudo-differential sense amplifier (SA) being identicalpseudo-differential sense amplifier circuits.
 3. A sense amplifiersystem according to claim 2, characterized in that eachpseudo-differential sense amplifier (RSA₁; RSA₂) circuit comprises inputdifferential pair transistors (402, 404) connected with a pair ofcascoded transistors (410, 412), and current source biasing pairtransistors cascoded (438, 440) with a pair of transistors (434, 436),said cascoding in each case increasing sense amplifier open-loop gain.4. A sense amplifier system according to claim 3, characterized in theinput transistors (402, 404) being p-channel transistors and the currentsource transistors n-channel transistors (438, 440), or vice versa.
 5. Asense amplifier system according to claim 2, characterized in that eachpseudo-differential sense amplifier circuit (RSA, SA) comprises asemi-balanced dual input (IN, IND) with a balanced dual output (OUTM,OUTP).
 6. A sense amplifier system according to claim 2, characterizedin that each pseudo-differential sense amplifier circuit (SA) comprisesa switched capacitor common feed-back loop (426, 428, 430, 432, 434,436, 438, 440) to control output common mode voltage.
 7. A senseamplifier system according to claim 2, characterized in that eachpseudo-differential sense amplifier circuit (SA) comprises means (430,432) for integral switched capacitor common mode self-bias generation.8. A sense amplifier system according to claim 2, characterized in thateach pseudo-differential sense amplifier circuit (SA) comprises anintegral positive feed-back latch (420, 422).
 9. A sense amplifiersystem according to claim 2, characterized in that eachpseudo-differential sense amplifier circuit (SA) comprises means forauto-zero offset cancellation.
 10. A sense amplifier system for sensingthe charges of a plurality of passive addressable charge-storing means(701), characterized in comprising at least two pairs of a first and asecond charge reference means (700) similar to the charge-storing means(701), said first charge reference means (700 _(−,1)) having theopposite polarization of the second charge reference means (700 _(−,2));each of said at least two pairs of charge reference means having acommon input node (WL) and a pair of common output nodes (RBL₁, RBL₂)respectively connected with said first and said second charge referencemeans (700) in each of said at least two pairs thereof, each commoninput node (WL) of said at least two pairs of charge reference means(700) moreover being connected with at least two charge-storing means(701); first and second pseudo-differential reference sense amplifiers(RSA₁; RSA₂) being respectively connected with the first common outputnode (RBL₁) and the second common output node (RBL₂) of the chargereference means (700), said first and second pseudo-differentialreference sense amplifiers (RSA₁; RSA₂) being adapted for generatingoutput reference signals to a common reference node (CHREF); and atleast two pseudo-differential sense amplifiers (SA), each having a firstinput (INP) connected with said common reference node (CHREF) forreceiving a common reference input signal and a second input (IN)respectively being connected with a common output node (BL) ofrespective one of said at least two charge storing means (701) forreceiving respective output signals therefrom, said at least twocharge-storing means (701) forming the elements of an orthogonal row andcolumn array thereof and with each of the charge-storing means of a rowbeing connected to one of said at least two common input nodes (WL) andeach of the charge storing means of a column being connected to a commonoutput node (BL); whereby each pseudo-differential sense amplifier (SA)is enabled to perform a threshold comparison and generating an outputsense signal indicative of a polarization state of a selectedcharge-storing means (700) connected therewith.
 11. A sense amplifiersystem according to claim 10, characterized in the common input nodes(WL) forming a portion of the word-line electrodes (WL) of amatrix-addressable array of charge-storing memory cells (700), thecommon output nodes (RBL) of the charge reference means (703) forming apair of reference bit-line electrodes (RBL₁, RBL₂) the common outputnodes (BL) of the charge storing means forming bit-line electrodes ofsaid matrix-addressable array; each of the reference bit-line electrodes(RBL₁, RBL₂) being assigned to the first and second pseudo-differentialreference sense amplifiers (RSA₁; RSA₂) respectively; and each of theother bit-line electrodes (BL) being assigned to one of thepseudo-differential sense amplifiers (SA), whereby in a readout cycle apolarization state of respective selected charge-storing memory cells(701) can be detected either sequentially or in parallel and comparedwith a reference value.
 12. A sense amplifier system according to claim11, characterized in the sense amplifier system being provided as asubblock (SB) in a block of more than one sense amplifier system of thiskind, such that the sense amplifiers (RSA, SA) of a subblock areassigned to a corresponding number of bit-line electrodes (BL) in thematrix-addressable array; and the pair of reference bit lines (P/RBL) ofrespective subblocks (SB) being distributed among the bit lines (BL) ofarray.
 13. A sense amplifier system according to claim 11, characterizedin that the sense amplifier system comprises a multiplexer (MUX)connected with the bit line electrodes (BL) of the matrix-addressablearray; a number k of consecutive bit lines (BL in the array defining asegment of all word-line electrodes therein (WL), said number k ofsegment-defining bit lines corresponding to the number ofpseudo-differential sense amplifiers (SA) in the sense amplifier system;and a pair of reference bit line electrodes (P/RBL) being providedadjacent to the bit line electrodes (BL) in each word line segment andconnecting pairs of reference charge storing means (700) in each wordline segment; whereby the charge-storing memory cells (701) on a singleword line electrode (WL) of a word line segment may be read in parallel,and all word line segments similarly in turn by applying an appropriateaddressing protocol and multiplexing the bit-line electrodes (BL) of aselected word line segment to establish their parallel connection torespective pseudo-differential sense amplifiers of the sense amplifier(SA) system as provided.
 14. A non-volatile passive matrix-addressablememory device comprising an electrically polarizable dielectric memorymaterial exhibiting hysteresis, particularly a ferroelectric or electretmaterial, wherein said memory material is provided in a layer contactinga first set and second set of respective parallel addressing electrodes(WL;BL), wherein the electrodes (WL) of the first set constitute wordlines of the memory device and are provided in substantially orthogonalrelationship to the electrodes (BL) of the second set, the latterconstituting bit lines of the memory device, wherein memory cells (801)with a capacitor-like structure are defined in the memory material atthe crossings between word lines and bit lines, wherein each memory cellcan be selectively addressed for a write/read operation via a word line(WL) and bit line (BL), wherein a write operation to a memory cell (801)takes place by establishing a desired polarization state in the cell bymeans of a voltage being applied to the cell via the respective wordline and bit line defining the cell, wherein said applied voltage eitherestablishes a determined polarization state in the memory cell (801) oris able to switch between the polarization states thereof, and wherein aread operation takes place by applying a voltage to the memory cell(801) and detecting at least one electrical parameter of an outputcurrent on the bit lines (BL), wherein a sense amplifier systemaccording to claim 11 is provided for sensing said polarization statesof said memory cells (801) during a read operation, and wherein saidmemory device is characterized in that said sense amplifier system is apseudo-differential sense amplifier system comprising at least onesystem subblock (SB), and that said at least one system subblock (SB)comprises at least one pseudo-differential sense amplifier circuit (SA)for sensing a polarization state of at least one memory cell (801)during said read operation and at least one pseudo-differentialreference sense amplifier circuit (RSA) for sensing a polarization stateof at least one reference memory cell (800) during said read operation,said at least one former circuit (SA) being connected with said at leastlatter circuit (RSA) via a common node (CHREF).
 15. A memory deviceaccording to claim 14, characterized in that said at least one systemsubblock (SB) comprises a plurality of said pseudo-differential senseamplifier circuits (SA) for sensing respective polarization states of acorresponding plurality of memory cells (801) during said readoperation.
 16. A memory device according to claim 14 or claim 15,characterized in that said at least one system subblock (SB) comprisestwo reference sense amplifier circuits (RSA₁, RSA₂) for sensing tworeference memory cells (800) during said read operation, said referenceferroelectric memory cells (800) having opposite polarization states.17. A memory device according to claim 16, characterized in that thefirst and the second reference sense amplifier circuits (RSA₁, RSA₂) areadapted for generating an average of a first and a second referencememory cell output signal to said common node (CHREF), and that said atleast one sense amplifier circuit (SA) connected therewith is adaptedfor comparing the output signal at said common node (CHREF) with theoutput signal from a memory cell (801).
 18. A memory device according toclaim 14, characterized in that said at least one sense amplifiercircuit (SA) and said at least one reference sense amplifier circuit(RSA) are realized with identical amplifier circuitry.
 19. A memorydevice according to claim 18, characterized in that said identicalamplifier circuitry (SA, RSA) comprises a reference side and an arrayside, said reference side mirroring the circuit structure of said arrayside.
 20. A memory device according to claim 14, characterized in thatsaid pseudo-differential sense amplifier system comprises a plurality ofsystem subblocks (SB).
 21. A memory device according to claim 20,characterized in that each subblock (SB) comprises a plurality of saidsense amplifier circuits (SA) for sensing the polarization state of acorresponding number of memory cells.